Quality & Test In Bare Board Manufacturing
An Introduction To Jtag/Boundary Scan
by Mario Berger, Göpel Electronic
Jtag/Boundary Scan is a test technology. It is the jump from physical access to a board’s conductor tracks (necessary for the In-Circuit Test) with all its physical limitations to an electric and, therewith, unlimited access. Jtag/Boundary Scan only requires four control lines and only a few important “Design for Testability” rules. When talking about Jtag or Boundary Scan, one refers to the IEEE Std. 1149.1 – thus the static, digital interconnection test. Its limitations are to be found in the analogue area as well as high-speed area. But brand-new approaches and solutions referring to the standards IEEE 1149.4 and 11149.6 have extended the utilisation of Jtag/Boundary Scan in these areas. A Boundary Scan test developer doesn’t have to deal with each and every detail of the technology since modern tools, based on component models, execute the greater part of his tasks. This article offers a short introduction and background to the technology and how it can be used.
PCB Fabrication
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Entry Board For HDI Microvia Drilling
by Thomas S. Michels, TMT Group of companies
The development of high performance electronic devices have resulted in the demand of high density of fine lines on the printed wire board and IC substrate, which leads to the decrease of hole size and the increase of hole number. However the traditional entry boards for drilling, such as Al foil or phenolic board, become less suitable for the drilling of small holes because of the high demand of drill quality and accuracy for the small holes. Therefore a new functional aluminum based entry board has been developed to enhance the accuracy of drill and to reduce the broken rate of the drill bit. Thus reducing the cost of drilling drastically. This article concentrates on the influence of entry boards and drills for HDI drilling and the influence of specialized entry boards for the drilling of filled and halogen-free laminates.
RFID Tags & Components
Accessory Materials
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Enabling Chemistries For 3D And Wafer-Level Packaging
by David Zoba and Russ Stapleton, Lord
The future of wafer-level packaging, especially those concerns related to die stacking, cost, small footprint, thin bond lines, fine pitch and reliability, are dependent on the evolution of key chemical technologies that specifically address the needs of the package and process. By understanding the functional chemistry in line with the material needs, a true wafer-level-applied die protection solution can be developed to provide the next level of critical cost/performance options to packaging engineers.
Assembly
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New Test Platform For Cleaning Process Development
by Mike Bixenman, Kyzen and Steve Stach, Austin American Technology
Innovative electronic assembly designs strive to increase functionality over smaller surface areas. Highly dense circuit assembly designs increase the cleaning challenge. Understanding the balance between static chemical and mechanical driving forces is fundamental to predicting and optimizing process variables. The objective of this research is to improve the science of cleaning under low standoff components.
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µCT For 3D Analysis Of Complex Assemblies
by Jon Dupree, Andreas Lechner, Yxlon International
With current and future advances in semiconductor packaging technology, a significant move from 2D to 3D X-ray inspection has to be expected to account for continued miniaturisation and expansion into the third dimension. Applications ranges from packaging analysis with the full assessment of wire bond alignment to solder integrity between stacked dies. Continuous growth in electric and electro-mechanical system complexity with increasing exploration of all three dimensions drive the need for 3D Microfocus computed tomography (µCT). Technological advances addressing major shortfalls of conventional time-consuming µCT inspections have reduced µCT inspection times from hours down to a couple of minutes.
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